Importance

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Abstract

In the preferred embodiment of the invention, a first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. A subtractor circuit subtracts the number of read clock pulses from the number of write clock pulses, and this difference is compared in a comparator circuit to determine if the difference is greater than a preset value. This determination provides the information as to the relative fullness of the FIFO. Specific flag values are user-programmed and are stored electronically as binary numbers in registers. The connection between individual subtractor circuits and individual comparator circuits for making the comparison is performed by a program select decoder which utilizes the difference output of the subtractor circuit and the flag program value.

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First Claim