Load reduced memory module and memory system including the same
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United States of America Patent
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Apr 16, 2013
Grant Date -
Dec 9, 2010
app pub date -
Jun 3, 2010
filing date -
Jun 5, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
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