SRAM speed and margin optimization via spacer tuning

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11508738
SERIAL NO

17036487

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Abstract

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An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lim, Kian-Long Hsinchu, TW 46 65
Lin, Chien-Chih Hsinchu, TW 76 274
Lin, Shih-Hao Hsinchu, TW 130 148
Su, Hsin-Wen Hsinchu, TW 80 202
Yang, Chih-Chuan Hsinchu, TW 85 82

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