TFT with reduced channel length and parasitic capacitance

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United States of America Patent

PATENT NO 5872370
SERIAL NO

08887899

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A thin film transistor (TFT) for a liquid crystal display (LCD) and method of making same is disclosed, the TFT having a source and drain electrode where at least one of the source and drain includes first and second conductive layers offset from one another by a distance .DELTA.L so that the resulting TFT channel length L.sub.T is equal to L.sub.T =L.sub.1,2 -.DELTA.L where L.sub.1,2 is either a channel length defined in the first conductive layer or a channel length defined in the second conductive layer. The TFT manufacturing process includes the steps of: a) providing a conductive gate layer and patterning same to form a gate electrode; b) depositing a substantially transparent conductive layer (e.g. ITO) and patterning same to form a pixel electrode; c) depositing and patterning a semiconductor layer (e.g. a-Si); a doped semiconductor contact layer; and a first source-drain conductive layer so as to form a TFT island or area; d) using a single photoresist to etch a channel in the first source-drain layer and a via in a gate insulating layer so as to expose the pixel electrode; and e) depositing and patterning a second source-drain layer over the via and the etched first source-drain layer so as to form a TFT with reduced channel length L.sub.T wherein the second source-drain layer contacts the pixel electrode through the via. At least one of, and preferably both, the source and drain electrodes include a portion of the first and second source-drain layers contacting but offset laterally from one another.

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Patent Owner(s)

  • FIRST CHICAGO/NBD BANK N.A.;INNOLUX CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boer, Willem den Troy, MI 40 2664
Gu, Tieer Troy, MI 38 1167

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