Inter-cluster communication network and heirarchical register files for clustered VLIW processors
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 2, 2010
Grant Date -
Jan 1, 2009
app pub date -
Jun 27, 2007
filing date -
Jun 27, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully