Organization of dirty bits for a write-back cache

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United States of America Patent

PATENT NO 7380070
APP PUB NO 20060184745A1
SERIAL NO

11060141

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Abstract

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A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit or a miss into the cache system has occurred. Further, the cache system comprises a data array into which cache lines of data are stored, each cache line comprising a plurality of sub-lines, and each sub-line is adapted to be written back to a system memory separate from the other sub-lines. The cache system also comprises a controller coupled to the tag and data arrays. The tag array includes a cache-line dirty bit associated with each cache line and the data array includes a plurality of dirty bits for each cache line. The plurality of dirty bits comprises one sub-line dirty bit for each sub-line.

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Patent Owner(s)

  • TEXAS INSTRUMENTS INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tan, Teik-Chung Austin, TX 19 331

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