Fault-tolerant multi-core microprocessing
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United States of America Patent
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Apr 17, 2007
Grant Date -
May 12, 2005
app pub date -
Oct 22, 2003
filing date -
Oct 22, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
One embodiment disclosed relates to a method of executing program code on a target microprocessor with multiple CPU cores thereon. One of the CPU cores is selected for testing, and inter-core context switching is performed. Parallel execution occurs of diagnostic code on the selected CPU core and the program code on remaining CPU cores. Another embodiment disclosed relates to a microprocessor having a plurality of CPU cores integrated on the microprocessor chip. Inter-core communications circuitry is coupled to each of the CPU cores and configured to perform context switching between the CPU cores.
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