Adder circuit and associated layout structure
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United States of America Patent
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Nov 12, 2002
Grant Date -
N/A
app pub date -
Oct 24, 1997
filing date -
Oct 29, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G0=g2+p2.multidot.g1+p2.multidot.p1.multidot.g0 /g0=/p2+/g2.multidot./p1+/g2.multidot./g1.multidot./g0 In other words, the block carry generation logic /G0 is produced by a single PMOS transistor, a series circuit formed of two PMOS transistors connected in series, and a series circuit formed of three PMOS transistors connected in series. The block carry generation logic G0 is produced by a single NMOS transistor, a series circuit formed of two NMOS transistors connected in series, and a series circuit formed of three NMOS transistors connected in series. Block carry generation logics can be formed in such a way as to achieve not only a reduction of the layout area but also a higher operation rate.
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