High-performance electrostatic clamp comprising a resistive layer, micro-grooves, and dielectric layer
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United States of America Patent
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Dec 19, 2006
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app pub date -
Apr 22, 2003
filing date -
Apr 22, 2003
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Abstract
An electrostatic clamp for securing a semiconductor wafer during processing. The electrostatic clamp includes a base member, a first dielectric layer, a second dielectric layer having a gas pressure distribution micro-groove network formed therein, a gas gap positioned between a backside of a semiconductor wafer and the second dielectric layer, and a pair of high voltage electrodes positioned between the first dielectric layer and the second dielectric layer.
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