Semiconductor memory device
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United States of America Patent
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Nov 26, 2019
Grant Date -
Sep 19, 2019
app pub date -
Aug 1, 2018
filing date -
Mar 16, 2018
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor memory device includes a memory string including a first select transistor, a first transistor adjacent to the first select transistor, and a memory cell transistor, a first select gate line, a first interconnect, a word line, a row decoder, a temperature sensor, and a control circuit. In the erase operation, the control circuit selects a first mode for applying a first voltage to the first interconnect when a temperature measured by the temperature sensor is equal to or higher than a first temperature, and selects a second mode for applying a second voltage to the first interconnect when the temperature measured is less than the first temperature.
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