Method for improving personal computer reliability for systems that use certain power saving schemes
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United States of America Patent
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Jan 21, 2003
Grant Date -
N/A
app pub date -
Dec 14, 1999
filing date -
Dec 14, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A periodic system 'wake-up' is implemented during S1, S2 or S3 states utilizing a hardware timer. A memory scrubbing routine is initiated that reads out all memory locations and writes back any memory locations that have single bit (correctable) Error Correction Code errors. This procedure minimizes the chances of a multiple bit error build up over time that may cause an unrecoverable error. The scrubbing routine is invoked whenever the system is brought out of S1, S2, or S3 state to insure that there are no single bit errors present when full system operation is resumed.
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