Memory architecture with pulsed-bias power

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United States of America Patent

PATENT NO 11468941
APP PUB NO 20220284942A1
SERIAL NO

17193632

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Abstract

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Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.

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Patent Owner(s)

Patent OwnerAddress
ARM LIMITEDCHERRY HINTON CAMBRIDGE CB1 9NJ

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Andy Wangkun Austin, US 86 160
Chong, Yew Keong Austin, US 96 322
Goberu, Penaka Phani Bangalore, IN 3 1
Srinivasa, Akash Bangalore Bangalore, IN 4 14

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