Circuit configuration for an integrated semiconductor memory with column access
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United States of America Patent
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-
Mar 18, 2003
Grant Date -
Sep 6, 2001
app pub date -
Dec 28, 2000
filing date -
Dec 28, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit configuration for an integrated semiconductor memory has memory cells which are configured in a matrix-type memory cell array and which are combined to form addressable units of column lines and row lines. A decoder for selecting one of the column lines with a column select signal has a terminal for an input signal for activating the column select signal. A row activation signal serves for activating a row access signal sequence. The terminal for the input signal of the decoder is connected to a signal from the row access signal sequence which indicates that the row access is concluded. Successive signals in the memory access process prevent the column access from taking place before the end of the row access. The memory access is controlled in a self-adjusting manner.
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