Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit manufacture
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United States of America Patent
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Jun 26, 2007
Grant Date -
Apr 20, 2006
app pub date -
Oct 18, 2004
filing date -
Oct 18, 2004
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Abstract
One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pattern, the silicon dioxide is etched to form a plurality of hemispherical microcavities in the silicon dioxide. Openings in the patterned nitride are filled, then another layer is formed over the silicon nitride layer using the silicon nitride as a support over the microcavities. An inventive structure resulting from the method is also described.
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