Clock and data recovery (CDR) architecture and phase detector thereof
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United States of America Patent
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Jun 4, 2013
Grant Date -
May 2, 2013
app pub date -
Oct 27, 2011
filing date -
Oct 27, 2011
priority date (Note) -
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Abstract
A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.
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