Method for forming strained channel PMOS devices and integrated circuits therefrom
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United States of America Patent
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Mar 8, 2011
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app pub date -
Dec 30, 2008
filing date -
Jan 21, 2008
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Abstract
, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).
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