Memory circuit testing system, semiconductor device, and memory testing method
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United States of America Patent
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Aug 18, 2009
Grant Date -
Nov 13, 2003
app pub date -
Jun 6, 2003
filing date -
Dec 8, 2000
priority date (Note) -
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Abstract
A semiconductor device that performs refresh tests of a plurality of individual memories built into the same chip and prevents excessive testing during the refresh test. When a first testing circuit enters a wait state, the first testing circuit issues a refresh command REF to a first memory circuit. Then, the first memory circuit refreshes the memory cells until a second testing circuit enters the wait state. That is, since the memory cells of the first memory circuit are refreshed until the writing to a second memory circuit ends, the refresh test time of the first and second memory circuits are the same.
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