Managing memory commands in a memory subsystem by adjusting a maximum number of low priority commands in a DRAM controller
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United States of America Patent
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Nov 16, 2021
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N/A
app pub date -
Jul 14, 2020
filing date -
Jul 14, 2020
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Abstract
A method is described for managing issuance of memory commands. The method includes determining whether a number of high priority commands from a cache controller meets a first threshold. In response to meeting the first threshold, a second threshold, which indicates a maximum number of low priority commands allowed in a low latency memory command queue, is set to a first value. In response to not meeting the first threshold, the second threshold is set to a second value. The method further selects a memory command for issuance from the cache controller command queue, wherein the memory command is a high priority memory command when the number of low priority memory commands stored in the low latency memory controller command queue meets the second threshold and is a low priority memory command when the number of low priority memory commands does not meet the second threshold.
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Patent Owner(s)
- MICRON TECHNOLOGY INC.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Isenegger, Laurent | Morgan Hill, US | 19 | 5 |
La, Fratta Patrick A | McKinney, US | 43 | 581 |
Walker, Robert M | Raleigh, US | 111 | 784 |
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