Electronic packages having multiple-zone interconnects and methods of manufacture

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6717066
APP PUB NO 20030103338A1
SERIAL NO

10004002

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, Yuan-Liang Chandler, AZ 73 1112
Vandentop, Gilroy J Tempe, AZ 23 406

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