Interrupt routing mechanism for routing interrupts from peripheral bus to interrupt controller
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United States of America Patent
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Oct 15, 2002
Grant Date -
N/A
app pub date -
Aug 25, 1999
filing date -
Aug 25, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An interrupt routing mechanism implemented in a host chipset to eliminate the need for the general purpose I/O pins, special software and external logic devices to steer particular interrupts from a non-legacy Peripheral Component Interconnect (PCI) bus to an external interrupt controller. Such an interrupt routing mechanism may be implemented by a series of logic gates such as OR gates and AND gates for combining all interrupts from a non-legacy PCI bus to produce an output boot interrupt to an external interrupt controller, and alternatively, implemented by a series of AND gates for combining all interrupts from a non-legacy PCI bus and a switch for forwarding an output boot interrupt to an external interrupt controller in accordance with a disable bit used for the steering function.
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