Split gate non-volatile memory cells with three-dimensional FinFET structure

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United States of America Patent

PATENT NO 10727240
SERIAL NO

16028244

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Abstract

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A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

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Patent Owner(s)

Patent OwnerAddress
SILICON STORAGE TECHNOLOGY INC450 HOLGER WAY SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Decobert, Catherine Pourrieres, FR 15 35
Do, Nhan Saratoga, US 211 997
Jourba, Serguei Aix en Provence, FR 14 28
Kim, Jinho Saratoga, US 335 2700
Liu, Xian Sunnyvale, US 92 851
Zhou, Feng Fremont, US 314 1405

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