Semiconductor manufacturing line availability evaluating system and design system
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United States of America Patent
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Jan 3, 2006
Grant Date -
May 19, 2005
app pub date -
Sep 24, 2004
filing date -
Sep 26, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An availability evaluation system of a semiconductor manufacturing line, comprising a unit configured to calculate an incidence probability Xi (i=1 to k) in combination by applying a tool operation probability and a tool stoppage probability to all combinations 'k' in which at least a line fabrication availability is not zero, of the combinations of operation and stoppage of tools, and by obtaining a product of the probabilities of all the tools, and a unit configured to, when a product between the incidence probability Xi of a combination and a fabrication availability Yi of the combination is defined as a probability converted fabrication availability with respect to each of the combinations, calculate an availability value of Q=Σ(i=1 to k)X1×Y1/F obtained by dividing a sum of probability converted fabrication availabilities of the combinations by a fabrication availability F at a 100% availability.
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