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United States of America Patent

PATENT NO 11581248
SERIAL NO

17224549

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Abstract

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A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

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Patent Owner(s)

  • SAMSUNG ELECTRONICS CO., LTD

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jang, Aenee Seoul, KR 16 10

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