Level translator circuit
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United States of America Patent
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Feb 15, 2011
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app pub date -
Aug 18, 2009
filing date -
Aug 19, 2008
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Abstract
A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit.
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