Semiconductor memory integrated circuit having high-speed data read and write operations
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United States of America Patent
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Nov 5, 2002
Grant Date -
Jun 6, 2002
app pub date -
Sep 26, 2001
filing date -
Dec 5, 2000
priority date (Note) -
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Abstract
Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.
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