Thin film transistor and fabricating method thereof having patterned active layer
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United States of America Patent
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Dec 26, 2000
Grant Date -
N/A
app pub date -
Oct 1, 1999
filing date -
Oct 2, 1998
priority date (Note) -
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Abstract
The present invention relates to a thin film transistor and a fabricating method thereof which is applied to a buried bus coplanar type TFT wherein the source and drain wires are located on a substrate. The present invention includes an insulated substrate, a source electrode and a drain electrode on the insulated substrate, a first insulating layer on the insulated substrate wherein the first insulating layer has a predetermined pattern, an active layer on the first insulating layer wherein the active layer has a source region, a channel region and a drain region, a second insulating layer covering the active layer, and a gate electrode on the second insulating layer over the channel region.
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