Arrangement and method for reducing the processing time of a data processing device
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United States of America Patent
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Jul 18, 2006
Grant Date -
Jul 3, 2003
app pub date -
Mar 20, 2001
filing date -
Mar 29, 2000
priority date (Note) -
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Abstract
The invention herein pertains to a data processing device (1) with a processor (2) and a memory (3). The memory (3) comprises a first memory sector (4) and a second memory sector (6), a first cache (5) being arrayed for the first memory sector (4) and a second cache (7) being arrayed for the second memory sector (6). It is the function of the second cache (7) that predetermined and selected sub-programs, interrupt vectors (8) and interrupt handlers (9), which are normally stored in the second memory sector (6), which is, for example, a ROM memory or a RAM memory, are saved in temporary storage in the second cache (7). It is an advantage that no displacement cycles take place in the second cache (7).
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