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Abstract

A semiconductor cell layout definition is used to define a semiconductor cell during a layout process of an integrated circuits. The semiconductor cell performs a logical function which is implemented by one or more interconnected transistors. The cell layout definition includes a layout pattern of the interconnected transistors, a transistor width input variable, a cell loading input variable and geometry data for the interconnected transistors. The geometry data for at least one of the transistors is a function of the transistor width input variable. The cell layout definition further includes a propagation delay which is a function of the transistor width and the cell loading input variables. The transistor width input variable allows the widths of the transistors in the cell to be optimized during the layout process to reduce timing violations and minimize power consumption.

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First Claim