Circuit and method for reducing power consumption in an instruction cache
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United States of America Patent
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Mar 18, 2003
Grant Date -
N/A
app pub date -
Sep 5, 2000
filing date -
Sep 5, 2000
priority date (Note) -
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Abstract
A circuit and method for reducing power in a memory, such as an instruction cache, having a number of blocks, are disclosed. A power reduction signal (also called a 'same block' signal) is generated. The power reduction signal indicates whether a subsequent instruction to be fetched from an instruction cache belongs in the same block as a previous instruction fetched from the same instruction cache. When the subsequent instruction belongs to the same block as the previous instruction, there is no need to perform a tag read or an instruction read from an instruction cache other than the same instruction cache which contains the block to which the subsequent instruction belongs, whereby a tag from a tag memory bank is not read when the power reduction signal is in a first logical state.
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