Bit-erasing architecture for seek-scan probe (SSP) memory storage

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United States of America Patent

PATENT NO 7750333
APP PUB NO 20080012094A1
SERIAL NO

11477276

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Abstract

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An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chou, Tsung-Kuan Allen San Jose, US 32 339
Ma, Qing San Jose, US 240 7075
Rao, Valluri R Saratoga, US 67 1139

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