Contact for vertical memory with dopant diffusion stopper and associated fabrication method
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United States of America Patent
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Aug 2, 2016
Grant Date -
Jun 16, 2016
app pub date -
Dec 16, 2014
filing date -
Dec 16, 2014
priority date (Note) -
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Abstract
A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via.
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