Importance

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Abstract

A method is provided which is applied to a logic block diagram, referred to as a block graph, which consists of a plurality of logic blocks interconnected by nets which carry logic signals between the logic blocks. The method is used to determine the characteristics of the given block graph, and more particularly to analyze the block graph to identify critical paths wherein logic signals must arrive at designated blocks at a critical time, and to determine whether the path delays of such critical paths are too long or too short. When critical paths are identified which have path delays that are too long or too short, the block graph can be redesigned to avoid such delays. The method includes three basic, broad steps each of which incorporates a plurality of subsidiary implementation steps. First, from the logic block graph, special blocks defined as storage elements because of their unique function are identified and classified as 'level zero' elements. Second, a procedure is carried out which 'levelizes' the remaining blocks in the block graph, that is, the blocks will be designated level two, level three, level four etc. in accordance with rules defined within the method. Finally, the long and short path delays, referred to as the extreme characteristics and identified by extreme values are determined for each block in level one, followed by a determination of the extreme characteristics of each block in level two, level three, etc. The extreme characteristics thus identify the critical paths within the logic block which are too long or too short so that a redesign can be made.

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First Claim