Data processing engine array architecture with memory tiles

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11296707
SERIAL NO

17196574

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Abstract

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An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

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Patent Owner(s)

  • XILINX INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Clarke, David Dublin, IE 119 1192
Date, Sneha Bhalchandra Santa Clara, US 8 13
Langer, Jan Chemnitz, DE 25 125
McColgan, Peter Dublin, IE 17 334
Noguera, Serra Juan J San Jose, US 38 271
Ozgul, Baris Dublin, IE 30 177
Rodriguez, Javier Cabezas Campbell, US 5 4
Tuan, Tim San Jose, US 49 518

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