Method for forming pinned photodiode resistant to electrical leakage
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United States of America Patent
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Sep 22, 2009
Grant Date -
May 29, 2008
app pub date -
Jan 29, 2008
filing date -
Dec 9, 2004
priority date (Note) -
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Abstract
A method is provided for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. An N+ region is implanted in a P-type substrate and a P-type well separates the N+ region from the shallow trench isolation (STI) structure. At least a P+ region is formed over the N+ region and overlapping at least part of the P-type well and a substrate portion between the N+ region and P-type well. The space between the N+ region and a damaged region adjacent the STI is greater than the expansion distance of the depletion region between the N+ region and the P-type well. The junctions of the various features are optimized to maximize a photosensitive response for the wavelength of the absorbed light as well as for reducing or eliminating electrical leakage.
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