Methods for reduced gate resistance FINFET
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United States of America Patent
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Jun 24, 2014
Grant Date -
Oct 31, 2013
app pub date -
Jun 26, 2013
filing date -
Dec 14, 2011
priority date (Note) -
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Abstract
Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed.
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