High speed clocked output driver for switching logic levels of an output pad at integer and integer and a half clock cycles
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 16, 1993
Grant Date -
N/A
app pub date -
Jul 10, 1991
filing date -
Jul 10, 1991
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An output driver and method including an output pad, for performing write operations from a central processor unit to a cache memory. The driver includes a pull-up circuit electrically connected to the output pad for switching the pad to a first logic state and a pull-down circuit electrically connected to the output pad for switching it to a second logic state. A plurality of signals are input to the pull-up and pull-down circuits to perform the switching of the output pad at integer and integer and a half clock cycles.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully