Logging of level-two cache transactions into banks of the level-two cache stores the transactions for diagnostic and debug
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United States of America Patent
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Mar 2, 2010
Grant Date -
Dec 6, 2007
app pub date -
Mar 12, 2007
filing date -
Jun 4, 2004
priority date (Note) -
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Abstract
A plurality of processor cores on a chip is operated in a normal fashion in a debug and diagnostic mode of operation of the processor. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache that is also on the chip. As data is passed from each of the processor cores through the crossbar switch to the L2 cache, the data in cached in a first plurality of banks of the L2 cache. The commands associated with the data and information concerning the status of the data in the level-one cache are logged in another plurality of banks of the L2 cache. This logged information can be readout and used in diagnosis and debugging of L1 and L2 cache problems.
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