Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques

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United States of America

PATENT NO 10546928
APP PUB NO 20190181228A1
SERIAL NO

15834721

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Abstract

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A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINE CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Balakrishnan, Karthik White Plains, US 334 2019
Hashemi, Pouya White Plains, US 599 4445
Khojasteh, Mahmoud Poughkeepsie, US 40 277
Reznicek, Alexander Troy, US 1406 11120

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