Wafer level chip scale package system
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United States of America Patent
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Sep 6, 2011
Grant Date -
Aug 2, 2007
app pub date -
Dec 29, 2006
filing date -
Jan 31, 2006
priority date (Note) -
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Abstract
A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.
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