Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
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United States of America Patent
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Sep 23, 2008
Grant Date -
Jun 5, 2008
app pub date -
Jan 15, 2008
filing date -
Jan 21, 2005
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Abstract
Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.
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