Latchup robust gate array using through wafer via
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United States of America Patent
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Mar 3, 2009
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N/A
app pub date -
Dec 14, 2007
filing date -
Dec 14, 2007
priority date (Note) -
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Abstract
A structure and a method for preventing latchup in a gate array. The structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.
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