Memory array and method used in forming a memory array comprising strings of memory cells
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United States of America Patent
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May 23, 2023
Grant Date -
May 12, 2022
app pub date -
Nov 6, 2020
filing date -
Nov 6, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
A memory array comprises a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material. The upper and lower conductor materials comprise different compositions relative one another. Laterally-spaced memory blocks individually comprising a vertical stack comprise alternating insulative tiers and conductive tiers, Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material. The channel material of the channel-material strings is directly electrically coupled to the upper and lower conductor materials of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.
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