Status flag handling in a digital data processing system
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United States of America Patent
Stats
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Jan 31, 1989
Grant Date -
N/A
app pub date -
Jul 29, 1986
filing date -
Jul 29, 1986
priority date (Note) -
Expired
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Abstract
Status flag handling method and apparatus for use in a digital data processing system provide error-resistant operation and simplicity. Two storage elements comprising one bit of a status register are operated such that: a reset places both elements in first predetermined states; a set flag operation places both elements in second predetermined states; a read flag operation alters the state of the second storage element; and a clear flag alters the state of the first storage element if and only if the state of the second storage element has previously been altered by a read flag operation. The flag output corresponds to the state of the first storage element. When implemented with single instructions, inadvertant flag negation and errors due to intervening interrupts are avoided. The read flag operation temporarily disables the set flag mechanism, protecting against setting the flag during a read operation. The flag is always read as asserted prior to being negated.
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Patent Owner(s)
- FREESCALE SEMICONDUCTOR, INC.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Shaw, Craig D | Austin, TX | 9 | 77 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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