Methods of forming a vertical transistor, methods of forming memory cells, and methods of forming arrays of memory cells
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United States of America Patent
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Jul 29, 2014
Grant Date -
Mar 13, 2014
app pub date -
Nov 14, 2013
filing date -
Feb 22, 2011
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
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