Method and system for virtual prototyping
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Nov 3, 2009
Grant Date -
May 16, 2002
app pub date -
Jun 1, 2001
filing date -
Jun 2, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.
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