Circuits and methods for processors with multiple redundancy techniques for mitigating radiation errors

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United States of America Patent

PATENT NO 8489919
APP PUB NO 20100268987A1
SERIAL NO

12626495

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Abstract

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Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.

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Patent Owner(s)

  • ARIZONA BOARD OF REGENTS;ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Clark, Lawrence T Phoenix, US 139 1967
Patterson, Dan W Scottsdale, US 9 149

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