Method of forming split gate memory cells with thinned side edge tunnel oxide

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11362218
APP PUB NO 20210399127A1
SERIAL NO

16910022

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Abstract

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A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

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Patent Owner(s)

  • SILICON STORAGE TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bertello, Bernard Bouches du Rhones, FR 3 2
Cuevas, Elizabeth Los Gatos, US 3 5
Decobert, Catherine Pourrieres, FR 15 35
Do, Nhan Saratoga, US 211 999
Festes, Gilles Fuveau, FR 4 3
Ghazavi, Parviz San Jose, US 8 17
Kim, Jinho Saratoga, US 337 2733
Thiery, Jean Francois Vaucluse, FR 2 0
Tkachev, Yuri Sunnyvale, US 16 355
Villard, Bruno Aix en Provence, FR 5 40

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