Optimizing IC clock structures by minimizing clock uncertainty
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United States of America Patent
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-
Apr 8, 2008
Grant Date -
Aug 24, 2006
app pub date -
Apr 11, 2006
filing date -
Jul 10, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
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