Interconnect structure with vias extending through multiple dielectric layers

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United States of America Patent

PATENT NO 11251127
APP PUB NO 20200126915A1
SERIAL NO

16722365

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Abstract

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An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chien-Han Nantou County, TW 14 19
Chiu, Chien-Chih Xinying, TW 31 87
Ho, Chun-Te Taipei, TW 9 21
Liang, Ming-Chung Hsinchu, TW 60 356

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