Importance

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Abstract

An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer. The alignment control logic includes predecoders for predecoding the instructions to provide instruction length information and pointer generation logic responsive to the instruction length information for generating a current instruction pointer for controlling transfer of instructions to the aligned instruction buffer.

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First Claim